基于延迟写回缓存的多粒度片上访存容错设计OA

On-chip memory is a critical component in modern microprocessor architectures,and its reliability and performance directly impact the stability and computational efficiency of the entire sys-tem.With the continuous increase in the integration density and memory access performance,on-chip memory faces significant challenges in achieving high reliability,high throughput,and energy-efficient design.While traditional coarse-grained access modes reduce error-tolerant redundancy and hardware overhead,their reliability and memory bandwidth perform poorly for applications with weak spatial locality.To address this,we propose a high-efficiency,fine-grained delayed write-back memory access error-tolerant design based on delayed write-back cache(DWB-cache).This design combines the low error-tolerance redundancy benefits of coarse-grained access with the performance benefits of fine-grained access,using DWB-cache to hide fine-grained data processing latency and balancing hardware overhead with access performance.We implemented FGDWB-ECC module in the M64-SM scalar memo-ry of a high-performance microprocessor,solving the DWB-cache consistency issue and determining the optimal cache depth.Experimental results demonstrate that,compared to the finest-grained error-tolerance baseline,FGDWB-ECC module achieves a 15.4%reduction in total area overhead and an 80.9%reduc-tion in redundant memory overhead.Moreover,application performance in both GEMM(good spatial locality)and FFT(poor spatial locality)remains on par with the baseline.