CMOS图像传感器低噪声低功耗读出电路研究OA

In order to reduce the conversion time and power consumption of the single-slope analog-to-digital converter(SS ADC)for low-noise CMOS image sensors,an SS ADC based on the small-range ramp coupling(SRC)technique is proposed.The proposed SRC technique combines the linear search algorithm with small-range ramp quantization to reduce the number of analog-to-digital conversion steps of the SS ADC while maintaining correlated multiple sampling(CMS)operation.The interval of the input signal is determined by the linear search algorithm,which prioritizes the code values of the K(K=log2M)high significant bits and reduces the power consumption of counter in the ramp quantization stage.The lower code values are obtained by multiple quantization with small-range slopes,and the number of quantization times is determined by the linear search results.The proposed SS ADC is designed with 0.11 μm CMOS process.Simulation results show that the differential nonlinearity(DNL)of this design is+0.5/-0.5 LSB,the integral nonlinearity(INL)is+0.3/-0.7 LSB,and the input-referred random noise is 127 μVrms.Compared with the SS ADC based on the conventional CMS technique(M=4),the proposed SRC technique can reduce the average energy consumption of the counter by 67.5%,the analog-to-digital conversion time by 56%and the power consumption by 40.8%.