基于FPGA的SSI绝对值编码器缺陷检测装置设计OA
Design of an FPGA-based SSI absolute encoder fault detection device
针对 SSI 绝对值编码器传统检测效率低、误判率高的问题,提出一种基于 FPGA 的自动化缺陷检测系统.系统采用 FPGA 与 STM32 双处理器协同架构,FPGA 实现 SSI 通信解析、数据采集及跳码、回码、死码等异常检测,STM32 负责步进电机控制与人机交互.结合编码增量动态阈值算法与高速缓存逻辑,实现编码器输出的实时分析与异常判定.实验结果表明,所提出系统具有较高的检测与识别精度,能够有效抵抗复杂环境干扰.该装置为工业现场编码器的高效、可靠检测及质量控制提供了一种低成本、高性能的解决方案.
To address the low efficiency and high false positive rates of traditional SSI absolute encoder testing,this paper presents an FPGA-based automated defect detection system.The system adopts a dual-processor architecture,integrating an FPGA and an STM32 microcontroller.The FPGA performs SSI communication parsing,data acquisition,and real-time detection of anomalies such as skip-ping,looping,and dead codes,while the STM32 handles stepper motor control and user interaction.By integrating the incremental dy-namic-threshold algorithm with high-speed buffering logic,the proposed system enables real-time analysis and accurate anomaly detec-tion of encoder outputs.Experimental results demonstrate that the proposed system achieves high detection and recognition accuracy and is capable of effectively resisting interference in complex environments.The proposed system offers a cost-effective,high-performance solution for efficient and reliable encoder inspection and quality control in industrial applications.
徐晨晨;赵忠鑫;王安红
临汾职业技术学院,临汾 041000||太原科技大学,太原 030000张家口摩术智能科技有限公司,张家口 075400太原科技大学,太原 030000
信息技术与安全科学
SSI绝对值编码器FPGASTM32双处理器架构编码增量动态阈值实时缺陷检测
SSI absolute encoderFPGASTM32dual-processor architecturecoded incremental dynamic thresholdreal-time defect detection
《集成电路与嵌入式系统》 2026 (9)
83-92,10
临职项目(2024YJKT-006)
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