应用于边缘视觉BNN推理的存算一体电路设计OA

With the rapid development of edge Artificial Intelligence(AI)technologies,resource-constrained terminals impose increasingly stringent requirements on the energy efficiency of neural network inference.However,existing multi-bit neural network models and their hardware implementations generally suffer from high power consumption and complex architectures,which limit their applicability in low-power scenarios.Therefore,this work focuses on the demand for lightweight inference in edge vision tasks and proposes a low-power computing-in-memory(CIM)circuit design for convolutional inference based on Binarized Neural Networks(BNNs).Based on the charge-domain coupling principle,a compact 10T1 C SRAM CIM cell is designed.To accommodate the analog output characteristics,a low-offset comparator and an efficient input driver circuit are further developed.In the proposed architecture,three convolutional lay-ers(Conv2～Conv4)of a five-layer BNN are mapped onto the CIM array to accelerate convolution operations in BNN inference.Mean-while,to avoid frequent off-chip memory accesses during multi-layer convolution processing,a sliding-window-driven data scheduling mechanism is adopted to complete the inference process.Implemented in a 180 nm TSMC process,the architecture achieves an average power consumption of 38.67 μW and an average energy efficiency of 243 TOPS/W,demonstrating strong potential for microwatt-level edge vision inference applications.