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基于改进三电平拓扑的SiC MOSFET串扰抑制电路设计OA

Design of SiC MOSFET Crosstalk Suppression Based on Improved Three-Level Topology

中文摘要英文摘要

碳化硅(SiC)MOSFET 因开关速度快等优势在电力电子变换器中得到应用广泛,但高 dv/dt 和 di/dt 易在半桥电路中引发串扰问题,导致器件误导通或损坏,从而制约其高频应用.现有串扰抑制方法存在牺牲开关速度、控制复杂或抑制效果单一等局限.针对上述问题,该文提出一种改进的串扰抑制电路:首先,在三电平电路基础上,增设由 N 沟道 MOSFET 与辅助电容串联的辅助支路,并提高关断负压,减小在中间电平钳位时间内驱动电阻的损耗,该支路无需额外控制信号,仅在器件关断时且关断电压未被抬升时导通,提供低阻抗路径分流米勒电流,在较高的关断负压下有效地实现了正向串扰抑制.然后,通过分析串扰产生的机理,详细地阐述了改进电路的工作模态及参数设计原则.最后,通过双脉冲测试验证表明:与传统驱动电路及三电平驱动电路相比,改进电路在保证开关速度的前提下,对正向串扰有较好的抑制效果,且减小了驱动电路在中间电平钳位时间内驱动电阻的损耗,有效平衡了串扰抑制效果与开关性能,提升了 SiC MOSFET 的工作可靠性.

Silicon carbide(SiC)MOSFETs are widely used in power electronic converters due to their advantages,such as high switching speed.However,high dv/dt and di/dt are prone to causing crosstalk in half-bridge circuits,leading to false turn-on or device damage.Existing crosstalk suppression methods have limitations,including reduced switching speed,complex control,or one-sided suppression.Therefore,this paper proposes an improved crosstalk suppression drive circuit.Building on the three-level circuit topology,the scheme introduces an auxiliary low-impedance branch composed of an N-channel MOSFET in series with an auxiliary capacitor.Because of its intelligent self-driving capability,the branch requires no additional independent control signals and operates automatically only when the power switch is off,thereby providing an efficient bypass path for the Miller current that causes forward crosstalk.Simultaneously,because this branch effectively manages forward crosstalk,the turn-off negative voltage can be reduced.This elevation significantly reduces conduction loss across the gate resistor during the intermediate-level clamping interval,achieving an optimal balance between loss and suppression performance. This paper begins with an in-depth analysis of the intrinsic mechanism of crosstalk generation in half-bridge circuits,detailing the paths of displacement current and their impact on the gate-source voltage during different switching transients.The operational principles of the proposed circuit throughout the entire switching cycle are provided using a stage-by-stage modal analysis.The study also offers design guidelines and a theoretical basis for key components.For instance,the value of the auxiliary capacitor must balance suppression effectiveness against its impact on switching characteristics,while the delay circuit's time constant must ensure that the clamping function activates within a safe timing window. Finally,experimental validation was conducted using a double-pulse test platform.The results demonstrate that,compared to conventional drive circuits and traditional three-level circuits,the proposed improved circuit maintains comparable switching speed and losses while exhibiting superior performance in suppressing the forward crosstalk voltage spike.Additionally,it effectively reduces gate resistor losses.This solution addresses the performance trade-off,providing a practical and efficient approach to enhance the operational reliability of SiC MOSFETs in high-frequency applications.

耿宇宇;苟鑫逸;曲昌琦

重庆理工大学电气与电子工程学院 重庆 400054重庆理工大学电气与电子工程学院 重庆 400054中国航空综合技术研究所 北京 100028

信息技术与安全科学

SiC MOSFET串扰抑制驱动电路双脉冲测试

SiC MOSFETcrosstalk suppressiondrive circuitdouble-pulse test

《电工技术学报》 2026 (16)

5495-5504,5534,11

重庆市自然科学基金面上项目(CSTB2023NSCQ-MSX0261)和重庆市教委科学技术研究项目(KJQN202401156)资助.

10.19595/j.cnki.1000-6753.tces.251570

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