HARLD:A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check DecodingOA
Low-density parity check(LDPC)decoding is an efficient error correction method in communication systems,especially in 5G networks,which require high performance and low latency;while common general-purpose architectures cannot meet the requirements.There has been some research on accelerating LDPC decoding,but the current methods still suffer from limitations in performance,flexibility,and communication cost.In this paper,we propose HARLD(Heterogeneous Architecture of RISC-V for LDPC Decoding),a tightly coupled heterogeneous computing architecture based on extended RISC-V for LDPC decoding,consisting of a CPU and a processing array.Compared with a loosely coupled System-on-Chip(SoC)-bus baseline,the tightly coupled design improves throughput by up to 32.4%and reduces average latency by up to 24.7%across evaluated configurations,while also enhancing resource and energy efficiency:processing element utilization up to 93.5%,instruction RAM utilization increased by up to 4.8x,and energy efficiency improved by up to 24.8%.At the system level,area and power are reduced by 17.6%and 10.2%,respectively,versus the loosely coupled design.
Bing Wang;Zi-Rui Ma;Hai-Bin Wu;Fu-Lin Zhang;Yue Wang;Zhi-Hua Fan;Wen-Ming Li;Xiao-Chun Ye;Dong-Rui Fan
China Mobile Research Institute,Beijing 100053,ChinaState Key Laboratory of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China University of Chinese Academy of Sciences,Beijing 100049,ChinaState Key Laboratory of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,ChinaState Key Laboratory of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China University of Chinese Academy of Sciences,Beijing 100049,ChinaState Key Laboratory of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China University of Chinese Academy of Sciences,Beijing 100049,ChinaState Key Laboratory of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China University of Chinese Academy of Sciences,Beijing 100049,ChinaState Key Laboratory of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China University of Chinese Academy of Sciences,Beijing 100049,ChinaState Key Laboratory of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China University of Chinese Academy of Sciences,Beijing 100049,ChinaState Key Laboratory of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China University of Chinese Academy of Sciences,Beijing 100049,China
信息技术与安全科学
tightly coupled heterogeneous computing architecturelow-density parity check(LDPC)decodingRISC-V extension
《Journal of Computer Science & Technology》 2026 (2)
P.774-790,17
supported by the National Key Research and Development Program of China under Grant No.2022YFB4501400the Institute of Computing Technology,Chinese Academy of Sciences-China Mobile Communications Group Co.,Ltd.Joint Institute,the Beijing Nova Program under Grant Nos.20220484054 and 20230484420the Beijing Natural Science Foundation under Grant No.L234078the State Key Laboratory of Processors SKLP。
评论