基于JTAG的非完全BS结构的SiP芯片内部互连测试OA

Boundary scan(BS)technology based on the joint test action group(JTAG)protocol enables interconnect testing.However,there is limited research on interconnect testing for bare dies in system-in-package(SiP)chips with incomplete BS scan structures.To address this issue,a testing method utilizing serial vector format(SVF)and boundary scan description language(BSDL)files is proposed.This method controls Flash devices without BS structures via a field-programmable gate array(FPGA)containing BS ports,verifying whether interconnects between bare dies in SiP chips function properly.Practical waveform validation confirms the feasibility of this approach.