超高频RFID芯片的电磁波能量获取电路研究与实现OA
Design and implementation of an energy harvesting circuit for UHF RFID chips
面向超高频射频识别(Radio Frequency Identification,RFID)芯片的应用需求,设计并实现了一种高效稳定的电磁波能量获取电路.该电路系统由整流电路、基准电路和稳压电路构成,旨在为芯片其他模块提供可靠电源.重点研究了差分整流电路在-11 dBm低输入功率下实现67%的转换效率及1.84 V输出电压;设计了超低功耗CMOS基准电路,其电压/电流温度系数分别低至34.9 ppm/℃和18.4 ppm/℃,电源抑制比(PSRR)在100 Hz时优于-93 dB;采用LDO结构的稳压电路,在负载变化时展现出良好的负载调整率(41.28 mV/mA).同时,设计了时钟、复位及解调和调制电路.该电路采用CMOS 180 nm工艺设计,版图面积为341 μm×346 μm.后仿真结果表明,整体功耗为6 μW.流片测试结果表明,各项性能指标均满足超高频RFID芯片对高转换效率和电源稳定性的要求.
This paper presents the design and implementation of a highly efficient and stable electromagnetic wave energy harvesting cir-cuit targeting ultra-high-frequency(UHF)RFID applications.The system consists of a rectifier,a reference circuit,and a voltage regu-lator,collectively providing a reliable power supply for other chip modules.Key achievements include a differential rectifier achieving 67%power conversion efficiency(PCE)with 1.84 V output at 11 dBm input power.An ultra-low-power CMOS reference circuit with temperature coefficients of 34.9 ppm/℃(voltage)and 18.4 ppm/℃(current),and a power supply rejection ratio(PSRR)better than-93 dB at 100 Hz.An LDO-based voltage regulator exhibiting a load regulation of 41.28 mV/mA under varying load conditions.Addi-tionally,clock,reset,demodulation,and modulation circuits are integrated.The circuit is implemented in a 180 nm CMOS process,occupying a layout area of 341 μm×346 μm.Post-layout simulations indicate a total power consumption of 6 μW.Silicon measure-ments confirm that all performance metrics meet the requirements for high conversion efficiency and power supply stability in UHF RFID chips.
李岩松;方洁虹;路旭东;吴静珠;肖宛昂
北京工商大学 计算机与人工智能学院,北京 100048中国科学院半导体研究所,北京 100083||中国科学院大学 集成电路学院,北京 100049北京工商大学 计算机与人工智能学院,北京 100048北京工商大学 计算机与人工智能学院,北京 100048中国科学院半导体研究所,北京 100083||中国科学院大学 集成电路学院,北京 100049
信息技术与安全科学
射频识别超高频整流电路基准电路稳压电路
RFIDUHFrectifier circuitreference circuitvoltage regulator circuit
《集成电路与嵌入式系统》 2026 (7)
54-64,11
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