基于CPU+FPGA SoC的卫星终端高速IP业务传输架构设计OA

Facing the processing performance bottleneck of current satellite communication terminals in high-throughput IP service sce-narios,this paper proposes a high-speed IP service transmission method based on a CPU+FPGA SoC architecture.The core of this method lies in the separation and cooperation of the control plane and the data plane.The functions required for high-speed data forwarding,such as IP access,route addressing,and link frame assembly/disassembly,are offloaded to the FPGA to form a high-performance data plane,control plane logic such as route maintenance and protocol interaction is handled by the CPU.Through key technologies of event-driven synchronization and hardware-level QoS scheduling,collaborative design challenges,including entry synchronization and low-la-tency signaling guarantee,are overcome.This achieves a significant performance leap on existing hardware,providing an effective solu-tion for the smooth performance upgrade of large-scale in-network satellite terminals and the design of compact,low-power terminals.