50 Gbit/s PON场景下高速LDPC编码器设计OA

[Objective]Low Density Parity Check(LDPC)codes have replaced Reed-Solomon(RS)codes as the Forward Error Correction(FEC)standard in 50 Gbit/s Passive Optical Network(PON)scenarios due to their near-Shannon-limit performance.However,their complex encoding and decoding matrices complicate the hardware implementation.[Methods]This paper im-proves the R.Urbanke(RU)encoding algorithm to support column swapping in the decoding matrix.We then design a three-stage pipelined high-speed encoder that reduces resource usage and latency,supports arbitrary code types,and robustly handles exceptions like loss indicators.[Results]Universal Verification Methodology(UVM)-based verification achieved 98%code cov-erage,confirming the encoder's ability to process the three protocol-specified code types and manage various exceptions.Field-Programmable Gate Array(FPGA)prototyping on the Intel Stratix 10 board showed that four encoders use only 14%of logical re-sources,achieving a data throughput of 50 Gbit/s.[Conclusion]This paper presents an improved RU encoding algorithm and a three-stage pipeline high-speed encoding architecture that achieves a data throughput of 50 Gbit/s with low latency and low re-source consumption in hardware implementation.The proposed solution can accurately handle all code types specified by the pro-tocol and effectively address various abnormal situations,providing an efficient and feasible approach for the hardware deployment of LDPC encoders in 50 Gbit/s PON scenarios,with significant application prospects.