基于现场可编程门阵列的硬件加速系统教学实验设计OA
Design of teaching experiment for hardware acceleration system based on field programmable gate array
电子设计自动化(EDA)技术课程是高等学校电子通信类专业的一门兼具高度专业性、应用性和实践性的专业课.现场可编程门阵列(FPGA)具有可编程性和灵活性,是该课程的硬件载体,可用于复杂系统和算法的实现,在人工智能、通信和医学等领域表现优异.针对现有 EDA技术课程实验在系统性与软硬件协同设计方面较为薄弱的问题,本文开展结合 FPGA 和人工智能算法的实验教学研究,通过设计基于 FPGA 的硬件加速系统,培养学生的系统级和软硬件协调设计能力,对电子信息类专业的 FPGA 实验和 FPGA 课程设计教学具有一定的参考意义.
Electronic design automation(EDA)technology course is a professional,applied and practical course for electronic communication majors in universities.Field programmable gate array(FPGA)with programmability and flexibility,as the hardware carrier of the course,can be applied to realizing complex systems and complex algorithms,and has excellent performance in various fields such as artificial intelligence,communication and medicine.To address the lack of systematic and hardware-software co-design in existing EDA course experiments,the research of the experiment teaching combining FPGA and artificial intelligence algorithms is carried out,and the design ability of the system-level and software-hardware coordination is cultivated by designing the FPGA-based neural network hardware acceleration system,which has certain reference significance for the FPGA experiment and the FPGA course design of the electronic information majors.
高家宝;苏婷
海南大学信息与通信工程学院,海口 570228海南大学信息与通信工程学院,海口 570228
电子设计自动化(EDA)技术现场可编程门阵列(FPGA)系统级软硬件协调
electronic design automation(EDA)technologyfield programmable gate array(FPGA)system levelsoftware-hardware coordination
《电气技术》 2026 (6)
49-53,5
海南省高等学校教育教学改革研究项目(Hnjg2025ZD-9)海南大学教育教学改革研究项目(hdjy2366)
评论