应用于反熔丝OTP的低功耗高速动态比较器OA

A high-speed,low-power improved StrongARM dynamic comparator was proposed to meet the requirements of anti-fuse One Time Programmable(OTP)memory for low-power,high-speed,and high-precision readout circuits.Based on the MSADLC architecture,the circuit was optimized by removing the tail current source and introducing a MOS transistor above the input differential pair to block the direct DC path from VDD to GND.A timing control mechanism was incorporated into the input stage to enhance gain and accelerate comparison speed.Additionally,a buffer circuit was integrated at the output node to enhance comparison precision.The design and tape-out verification were implemented using the SMIC 28 nm CMOS process.Simulation results demonstrate that the comparator achieves a power consumption of 36.26 μW,a delay of 63 ps,and an offset voltage of 3.66 mV,exhibiting superior performance compared to traditional StrongARM and MSADLC structures.Measurement results indicate that the OTP equipped with this dynamic comparator achieves a 73.2%reduction in read time,a 64.2%reduction in power consumption,and a 2.07%increase in read accuracy.