面向RDMA远内存的变粒度硬件DRAM缓存设计OA

Memory disaggregation is a cost-effective approach to improve memory utilization in datacenters.Current im-plementations of memory disaggregation systems can be categorized into two software-based approaches and one hardware-based approach,all of which leverage local memory to mitigate the long latency overhead of accessing re-mote direct memory access(RDMA)by caching hot data.Among these,the memory-semantic-interconnect-based hardware approach offer several promising advantages,including low latency and application transparency.Howev-er,constrained by hardware logic complexity and timing limitations etc.,existing hardware dynamic random access memory(DRAM)cache designs employ simplistic structures with fixed or dual caching granularities,failing to full-y exploit the memory access semantics of running applications and consequently delivering optimal performance across diverse workloads.Based on analysis of preliminary design's shortcomings and two observed application memory access patterns,this paper proposes a novel hardware DRAM cache design that performs real-time analysis of application memory access patterns and dynamically selects optimal prefetching and caching granularities.The core innovations include two aspects.(1)Correlation-based prefetching mechanism:analyzing the access correla-tions among multiple fine-grained data blocks to determine the granularity of data objects accessed by applications,enabling prefetching of multiple strongly correlated fine-granularity blocks.(2)Dual-track eviction policy:apply-ing least recently used(LRU)algorithm among limited candidates and'hotness'-aware Clock algorithm for two eviction scenarios.Based on our evaluations using the DRAMSim3 simulator,it exhibits a performance speedup ranging from 1.12×to 1.43×against the state-of-the-art hardware DRAM cache designs.