首页|期刊导航|空天预警研究学报|基于RFSoC的超宽带雷达信号多数据率抽取算法实现

基于RFSoC的超宽带雷达信号多数据率抽取算法实现OA

Implementation of RFSoC-based multi-data-rate decimation algorithm for ultra-wideband radar signals

中文摘要英文摘要

针对超宽带雷达在高采样率场景下吉比特级原始数据的处理瓶颈,以及传统多相滤波抽取技术在速率切换灵活性、硬件资源消耗、跨时钟域时序协同方面的固有局限,提出一种基于射频片上系统(RFSoC)的动态多数据率抽取算法.该算法利用RFSoC片内的超级运算单元(SuperDSP),结合多相并行滤波模式完成抗混叠滤波与抽取.实测结果表明,该算法可实现 2.4 GS/s同相正交(IQ)信号1~8 倍抽取,切换时间低至 40 ns,带外抑制优于 40 dB,现场可编程门阵列(FPGA)辑资源使用率显著降低,且无额外数字信号处理器(DSP)资源消耗.本文方案为超宽带雷达多模式自适应处理提供了兼具工程可行性与性能优势的技术路径.

In order to address the processing bottleneck of gigabit-level raw data for ultra-wideband radar in high sampling rate scenarios,as well as the inherent limitations of traditional polyphase filtering decimation tech-nologies in rate switching flexibility,hardware resource consumption and cross-clock domain timing coordination,this paper proposes a dynamic multi-data-rate decimation algorithm based on radio frequency system-on-chip(RF-SoC).This algorithm utilizes the super digital signal processor(SuperDSP)within the RFSoC and combines the polyphase parallel filtering mode to complete anti-aliasing filtering and decimation.The actual test results demon-strate that the proposed algorithm can achieve 1-to-8 decimation for 2.4 GS/s in-phase/quadrature(IQ)signals,with a switching time as low as 40 ns and out-of-band suppression better than 40 dB,and that the logic resource utilization rate of field programmable gate array(FPGA)is significantly reduced with no additional resource con-sumption in digital signal processor(DSP).The scheme proposed in the paper provides a technical path with both engineering feasibility and excellent performance for multi-mode adaptive processing of ultra-wideband radar.

彭小镔;邢小明;盛世威;彭霞

南京电子技术研究所,南京 210039南京电子技术研究所,南京 210039南京电子技术研究所,南京 210039南京电子技术研究所,南京 210039

信息技术与安全科学

超宽带雷达多数据率抽取射频片上系统动态系数加载抗混叠滤波

ultra-wideband radarmulti-data-rate decimationradio frequency system-on-chipdynamic co-efficient loadinganti-aliasing filtering

《空天预警研究学报》 2026 (2)

86-90,94,6

10.3969/j.issn.2097-180X.2026.02.002

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