亿门级FPGA互连线资源测试方法研究OA

In order to solve the problem that the interconnection line resources of billion-gate level FPGA cannot be tested,this article proposes a global interconnection line routing method based on the TCL command line and the internal resource structure of billion-level FPGA.The interconnection line resource test design problem cannot be implemented in the development environ-ment Vivado,and the look-up table is used as a relay unit to compensate for the driving capability and extended routing direction,and ATE is used to complete test verification and automated testing.This method has good convenience and controllability whether it is used for automated mass production test vector design or interconnect line fault diagnosis.