基于FPGA的新型自校准高分辨率DPWM设计OA

DPWM is the core of digital control switching power supply.To address the conflict between the high resolution of DPWM and the system operating frequency,this paper designs a high-resolution DPWM scheme based on FPGA.A 4 ns 14 bit low-resolution delay unit is implemented based on the traditional counter-comparator structure,and a 100 ps 7 bit high-resolution delay unit is achieved using a carry delay chain.The novel hybrid structure proposed in this paper can independently adjust the high-resolution delay of the rising and falling edges and has a real-time self-calibration unit to ensure the adjustment accuracy of the delay line and prevent the gradient adjust-ment from crossing the low-resolution period and causing offset stability issues.This architecture uses a cascaded carry delay chain de-sign and global PWM drive via a BUFG,enabling automatic global routing and improving system portability.The experiment results demonstrate that the high-resolution delay units of this architecture are all below 100 ps,with an average delay of 67 ps,and it has high linearity and monotonicity.