融合XADC反馈与超时响应的JESD204B IP核优化设计OA
Optimized design of JESD204B IP core integrating XADC feedback and timeout response
JESD204B接口协议的链路建链稳定性是保障高速数据通信可靠性的核心前提,对提升高速数据采集传输系统的性能具有重要意义.针对传统JESD204B IP核在高低温等恶劣环境下链路建链成功率低、故障定位效率差的问题,提出一种兼顾环境适应性与可调试性的JESD204B IP核优化方案.采用分层优化策略,在JESD204_phy核中引入XADC温度采集模块,根据实时温度区间动态配置高速接口参数,提升链路抗温度漂移能力;在JESD204_core核中增设链路建链超时响应模块,通过错误类型分类统计与有序复位控制避免建链超时导致的链路阻塞,并为故障定位提供量化依据.搭建"ADC+FPGA"数据采集传输验证系统架构,在-55~125℃宽温范围内测试.实验结果表明,在极限高低温工况下链路建链成功率较传统方案提升约8%,且能有效定位故障原因,验证了该优化IP核的高可靠性与工程实用性,可满足恶劣环境下的高速数据传输需求.
The stability of link establishment in the JESD204B interface protocol is a core prerequisite for ensuring the reliability of high-speed data communication,and it is vital for enhancing the performance of high-speed acquisition and transmission systems.To address the low link establishment success rates and inefficient fault localization of traditional JESD204B IP cores in harsh environments such as extreme high and low temperatures,this paper proposes an IP core optimization scheme to balance environmental adaptability and de-buggability.This scheme adopts a hierarchical optimization strategy,introducing an XADC temperature acquisition module into the JESD204_phy core to dynamically configure high-speed interface parameters based on real-time temperature ranges,thereby enhancing the link's resistance to temperature drift.Additionally,a link establishment timeout response module is added to the JESD204_core core,which avoids link blockage caused by timeouts through error type classification statistics and ordered reset control,and provides a quantitative basis for fault localization.A verification system architecture of"ADC+FPGA"for data acquisition and transmission is con-structed,and tests are conducted within a wide temperature range of-55℃to 125℃.The test results show that the link establish-ment success rate under extreme temperature conditions is improved by approximately 8%compared to the traditional scheme.Further-more,the optimized IP core effectively locates the cause of faults,verifying its high reliability and engineering practicality,which meets the high-speed data transmission requirements in harsh environments.
谢达;于宗光;范继聪;曹正州;单悦尔
中国电子科技集团公司第五十八研究所,无锡 214000中国电子科技集团公司第五十八研究所,无锡 214000中国电子科技集团公司第五十八研究所,无锡 214000中国电子科技集团公司第五十八研究所,无锡 214000中国电子科技集团公司第五十八研究所,无锡 214000
信息技术与安全科学
JESD204BIP核链路建链XADC超时响应
JESD204BIP corelink establishmentXADCtimeout response
《集成电路与嵌入式系统》 2026 (5)
30-37,8
国家重点研发项目课题工艺协同设计(STCO)方法研究—AI芯片的STCO方法验证(2024YFB4405405)江苏省自然科学基金前沿引领技术基础研究项目—跨维度、多功能功能异构集成芯粒基础技术研究(BK20232029)
评论