Effects of cell topology and JFET width on depletion layer of SiC MOSFETOA
Effects of cell topology and JFET width on depletion layer of SiC MOSFET
Bofeng Zheng;Houcai Luo;Huan Wu;Jingping Zhang;Xianping Chen
Key Laboratory of Optoelectronic Technology&Systems,Chongqing University,Chongqing 400044,ChinaKey Laboratory of Optoelectronic Technology&Systems,Chongqing University,Chongqing 400044,ChinaKey Laboratory of Optoelectronic Technology&Systems,Chongqing University,Chongqing 400044,ChinaKey Laboratory of Optoelectronic Technology&Systems,Chongqing University,Chongqing 400044,ChinaKey Laboratory of Optoelectronic Technology&Systems,Chongqing University,Chongqing 400044,China||Key Laboratory of Power Transmission Equipment&System Security and New Technology,Chongqing University,Chongqing 400044,China
4H-SiCdepletion layergate oxide capacitanceJFET regionreliability
4H-SiCdepletion layergate oxide capacitanceJFET regionreliability
《半导体学报（英文版）》 2026 (4)
65-76,12
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