时钟稳定性研究OA

The 125 MHz clock jitter generated by the FPGA loopback will be aggravated after being kept in the low tempera-ture environment of-40℃for 1 hour,which affects the establishment of the link of the recording equipment and the accuracy of data acquisition and storage,and brings serious impact on the reliability of the system.To address this problem,the solution of adding CDCM61004 clock chip instead of MMCM to generate high-speed clock on the hardware of the acquisition device is proposed.Tak-ing into account the demand for miniaturization of storage devices,on the premise of not increasing the size and cost of the device,the use of software means to reduce clock jitter by upgrading the 3-stage PLL filtering on the basis of DCM.After several experi-ments in-40℃low temperature environment,the optimized and upgraded recording device has no unsuccessful link establishment and data error code phenomenon,which confirms the feasibility of the solution.