基于环形放大器的高能效12位200 MS/s流水线逐次逼近型模数转换器设计OA

This study proposes a 12b 200 MS/s pipeline successive approximation analog-to-digital converter(Pipeline SAR ADC)for 5G and Wi-Fi 6E wireless communication applications.To address drawbacks such as slow speed and high power consumption in the residue amplifiers of conventional Pipeline ADC,a pseudo-differential switched-capacitor amplifier based on a self-biased ring amplifier is designed.This design incorporates a reference voltage-halving technique in the second stage to reduce the system power consumption and enhance the overall speed.For traditional gate-bootstrapped switches,optimizations for speed and partial compensation of clock feedthrough effects are implemented.In addition,a set-reset(SR)latched data register is proposed to accelerate the logic circuitry of the SAR ADC.The ADC is designed using a 55 nm CMOS process with a core area of 0.182 mm2.The simulation results show that at 27℃and a 1.2 V supply voltage,the signal-to-noise distortion ratio(SNDR)was 72.93 dB,the power consumption was 9.28 mW,and the Schreier figure of merit(FoMS)was 173.25 dB,at an input signal frequency of 97.85 MHz.