一种宽带低偏流轨对轨运算放大器设计OA

A two-stage operational amplifier with low input bias current,rail-to-rail input,high gain,and high bandwidth has been de-signed.This design combines a folded-cascode first stage with a class-AB output stage,incorporating a linear transconductance(Gm)loop and gain-boosting techniques.The first stage employs a folded-cascode architecture,achieving rail-to-rail input through parallel NMOS and PMOS input differential pairs.A dedicated current compensation scheme ensures a constant output impedance of the first stage.The second stage utilizes a class-AB output configuration,where a translinear loop precisely sets the quiescent current of the out-put stage,resulting in improved drive capability and reduced power consumption.Gain-boosting techniques are applied to further en-hance the output impedance of the cascode structure,thereby increasing the overall DC gain.The op-amp is fabricated in a SMIC 180 nm MS BCD CMOS process.After tape-out,a test platform is independently developed by designing the test circuitry and fabricating a cus-tom PCB board.Key parameters of a broadband low-input-bias-current operational amplifier,including input bias current,offset volt-age,open-loop gain,small-signal bandwidth,slew rate,and noise,are measured using an oscilloscope,network analyzer,and spectrum analyzer.Test results demonstrate that with a 2 pF load capacitor,the amplifier achieves a low-frequency gain of 90 dB and a gain-band-width product(GBW)of 380 MHz.