面向SoC内存的流水线奇偶校验电路设计与优化OA

As SoC architectures evolve to meet the computational intensity of diverse AI applications,the pursuit of high-performance throughput must be balanced with uncompromising reliability.Consequently,parity check mechanisms have emerged as a cornerstone of modern circuit design,essential for safeguarding the integrity of massive data movement within the SoC fabric.However,in wide-bit-width data transmission scenarios,traditional parity check circuit designs face challenges such as high verification complexity and signifi-cant decoding latency,which in turn constrain the overall performance of SoCs,including system master clock frequency and data access bandwidth.To address this technical challenge,this paper innovatively proposes a multi-stage pipelined parity check circuit design method for the AXI bus in SoC memory.This design employs a pipelined architecture to optimize the verification process in stages,sig-nificantly reducing the critical path delay in the data pathway.The experiment results demonstrate that,at a minimal cost of a 0.47%increase in total circuit area and a 0.24%rise in power consumption,the proposed design method achieves timing optimization of the date read/write bus critical path,reducing the maximum delay of the AXI bus write and read data circuit paths by 18.62%and by 25.60%respectively,effectively enhancing the overall performance and reliability of the SoC.