一种无片外电容的高PSR瞬态增强型LDOOA

To address the poor power supply rejection(PSR)of conventional capacitorless low-dropout regulators(LDOs)in the mid-to-high frequency range,a capacitor-compensated current-mode feedforward ripple cancellation(CFFRC)circuit was designed.A fully balanced tunable pseudo-resistor-based active low-pass filter was utilized to achieve a low-cutoff frequency of less than 100 Hz with minimal layout area,resulting in a PSR improvement of more than 20 dB in the 10 kHz-1 MHz frequency range.Furthermore,to enhance the transient response capability of the capacitorless LDO,a differential transient enhancement architecture was proposed.This structure also functions as a frequency compensation structure,providing an additional zero that increases the phase margin.The LDO was designed and verified based on a 180 nm CMOS process.Simulation results show that the PSR reaches-94.6 dB at 100 kHz under light load conditions.When the load current steps from 1 mA to 100 mA within 1 μs,the output overshoot and undershoot voltages are 92 mV and 67 mV,respectively.Compared to the unimproved LDO,the overshoot and undershoot voltages are reduced by 205 mV and 148 mV,respectively.The phase margin remains above 48° under all load conditions,satisfying stability requirements.