基于双重噪声抵消的宽带低噪声放大器设计OA

To break the trade-off between noise figure(NF)and power consumption in traditional noise-canceling low-noise amplifiers(LNAs),a wideband LNA was designed using on the SMIC 65 nm process,covering a bandwidth of 0.2-6.0 GHz.This LNA adopted a dual-path noise-cancelling structure,which can effectively reduce the amplifier's noise figure while maintaining low power consumption.To further reduce the quiescent power consumption,an NMOS-PMOS complementary transistor topology was employed.Measurement results indicate that within the operating frequency band,the amplifier achieves a gain of 14-16 dB,a noise figure of 3.5-4 dB,and an input third-order intercept point(IIP3)ranging from 2 dBm to 3.5 dBm,with a total quiescent current of only 4 mA.Compared with other state-of-the-art designs,the proposed LNA has the advantages of low power consumption,low noise figure,and compact chip area.