集成电路下基于BST-SALT算法的时钟树优化技术OA

With the continuous miniaturization of integrated circuit process nodes and the continuous growth of design scale,clock tree synthesis faces severe challenges in timing convergence,power consumption control and signal integrity.Aiming at the problem of difficult global balance between clock bias constraints,path delay optimization,and resource efficiency in traditional methods,a hybrid algorithm based on bounded bias tree and Steiner shallow light tree fusion is proposed.By introducing an insertion delay estimation model and a key line length model,a clock tree optimization model is constructed.The experimental results show that the proposed clock tree optimization model reduces the maximum path delay(79 ps)of the clock tree by 14.13%compared to the traditional delay merging embedding algorithm(92 ps).In industrial scenarios such as automotive grade chips and 7 nm mobile SoCs,the dynamic power consumption is only 2.30 mW/MHz.The research provides a global optimization solution that balances timing,power consumption,and area for high-performance and low-power chip design,offering a new approach for improving heterogeneous integration and advanced packaging technologies.