基于自适应迭代的软硬模块混合布图面积最小化启发式方法OA

As the complexity of integrated circuit design increases,how to effectively arrange functional modules within the limited chip area to enhance resource utilization has become a significant research topic in the field of electronic design automation.To address the mixed soft-hard module floorplanning area minimization problem in integrated circuit floorplanning and enhance layout compactness,a heuristic algorithm based on adaptive iteration is proposed.The algorithm employs a hierarchical enumeration strategy to generate module combinations and decomposes the problem into a series of hard module area minimization subproblems.During the iterative process,the algorithm adaptively selects appropriate subproblems for computation and improves floorplanning quality by integrating the skyline heuristic method with a local search strategy.Additionally,a memory pool strategy is introduced to further expand the solution search space.The experimental results demonstrate that the proposed method achieves an average fill rate of over 98％under varying proportions of soft modules.Among the 11 test instances containing hard modules,8 instances exhibit a slightly higher filling rate than those achieved by related algorithms in the literature.