Optimizing 55 nm split-gate memory for compute-in-memory:a focus on floating-gate engineeringOA
Optimizing 55 nm split-gate memory for compute-in-memory:a focus on floating-gate engineering
Wanyi Ling;Xuan Li;Dertsyr Fan;Ichun Chuang;Tzung Wen Cheng;Chenming Tsai;Dawei Gao;Ranran Liu;Kun Ren;Dianyu Qi;Yongyu Wu;Guangji Li;Miao Zhou;Qingshuang Xu;Zhenghui Xia
College of Integrated Circuits,Zhejiang University,Hangzhou 310000,ChinaZhejiang ICsprout Semiconductor,Hangzhou 311200,ChinaIOTMemory Technology Inc.,Taipei City 10592,ChinaIOTMemory Technology Inc.,Taipei City 10592,ChinaIOTMemory Technology Inc.,Taipei City 10592,ChinaIOTMemory Technology Inc.,Taipei City 10592,ChinaCollege of Integrated Circuits,Zhejiang University,Hangzhou 310000,China||Zhejiang ICsprout Semiconductor,Hangzhou 311200,ChinaCollege of Integrated Circuits,Zhejiang University,Hangzhou 310000,ChinaCollege of Integrated Circuits,Zhejiang University,Hangzhou 310000,ChinaCollege of Integrated Circuits,Zhejiang University,Hangzhou 310000,ChinaZhejiang ICsprout Semiconductor,Hangzhou 311200,ChinaZhejiang ICsprout Semiconductor,Hangzhou 311200,ChinaZhejiang ICsprout Semiconductor,Hangzhou 311200,ChinaZhejiang ICsprout Semiconductor,Hangzhou 311200,ChinaZhejiang ICsprout Semiconductor,Hangzhou 311200,China
split-gatefloating-gate55 nm technology nodecomputation-in-memory
split-gatefloating-gate55 nm technology nodecomputation-in-memory
《半导体学报（英文版）》 2026 (3)
46-53,8
This paper was supported by National Key Research and Development Program of China(2022YFF0605803),Zhejiang key R&D project(2023C01017),and the Zhejiang Key Research and Development Project(2024SJCZX0030).Thanks Zhejiang Technology Innovation Center of CMOS IC Manufac-ture Process and Design for supporting us to do this research.
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