一种高电源抑制比低功耗LDO设计OA

In order to meet the requirements of radio frequency(RF)circuits for high power supply rejection(PSR)and low power consumption in the mid-to-high frequency range,this paper proposed a low-dropout regulator(LDO)design featuring both high power supply rejection ratio and low power consumption.By introducing a low-output-impedance buffer and an adaptive dynamic zero compensation circuit between the output of the error amplifier and the gate of the power transistor,the system stability was ensured while extending the PSR bandwidth,thus achieving high power supply rejection characteristics in the mid-to-high frequency range.The adoption of a buffer that combines fixed bias and adaptive bias,together with a sub-threshold CMOS reference with lower static current,effectively reduced the overall power consumption of the circuit.The proposed circuit was designed based on the SMIC 55 nm CMOS process,supporting an overall supply voltage range of 1.7-3 V,an output voltage of 1.2 V,and a load current range of 500 μA-50 mA.Experimental results indicate that when the load current is 50 mA,the LDO achieves a PSR of-61.2 dB at 100 kHz and-63 dB at 1 MHz,with a minimum quiescent current of only 40.4 μA.This LDO is therefore suitable for electronic devices sensitive to power supply ripple.