基于锁相环的Flash FPGA时钟网络架构设计OA
Design of a Phase-Locked Loop-Based Flash FPGA Clock Network Architecture
设计一种基于锁相环(PLL)的Flash FPGA时钟网络架构,该架构的全局时钟增加至3个,核心输出时钟额外增加2个,在芯片四周设计了 1个带PLL的时钟调节电路和5个不带PLL的时钟调节电路,用于实现分频、倍频、相移和延时功能.仿真结果表明该架构可以满足整个芯片的时序配置需求.流片测试结果表明该架构的最高工作频率可达350MHz,较原设计的时钟调节电路(180 MHz)有显著提升,达到国外同规模类型产品的水平.
A Flash FPGA clock network architecture based on phase-locked loop(PLL)is designed.The number of global clocks is expanded to three,and two additional core-output clocks are added in this architecture.One PLL-equipped clock conditioning circuit and five non-PLL clock conditioning circuits are implemented around the chip periphery to achieve frequency division,frequency multiplication,phase shift,and delay functions.Simulation results demonstrate that this architecture can meet the timing configuration requirements of the entire chip.Actual tape-out tests indicate that the maximum operating frequency of the architecture reaches 350 MHz,a significant improvement over the original clock conditioning circuit(180 MHz)and comparable to that of similar-scale international products.
王雪萍;蔡永涛;张长胜;马金龙
中国电子科技集团公司第五十八研究所,江苏无锡 214035中国电子科技集团公司第五十八研究所,江苏无锡 214035中国电子科技集团公司第五十八研究所,江苏无锡 214035中国电子科技集团公司第五十八研究所,江苏无锡 214035
信息技术与安全科学
Flash FPGA锁相环时钟网络
Flash FPGAphase-locked loopclock network
《电子与封装》 2026 (1)
57-61,5
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