基于Gm-TIA架构的100 Gb/s SerDes接收前端设计OA

This paper presents an analog front-end circuit for high-speed SerDes receivers,designed to address varying channel losses.Utilizing a transconductance-transimpedance(Gm-TIA)architecture,the circuit implements a continuous-time linear equalizer(CTLE)with a tunable peaking gain of 2.2～12.5 dB at the Nyquist frequency and a variable gain amplifier(VGA)with a gain range of-8～3.5 dB,offering flexibility for different channel characteristics.A complementary transconductance stage is employed to achieve current reuse,enhancing transconductance and power efficiency.A T-coil structure is designed to achieve broadband impedance matc-hing,considering parasitics from ESD,pads,and AC-coupling.Inductive peaking and tunable MOS resistors are adopted to extend bandwidth and enable continuous gain tuning.Fabricated in a 65 nm CMOS process,post-layout simulations show that the front-end achieves a peaking gain of 1.1～11.5 dB at 25 GHz Nyquist frequency,supports 100 Gb/s PAM4 signal transmission,and consumes 12.83 mW under a 1.2 V supply.