VeriOptima:基于两阶多智能体的电路设计与优化AI框架OA

To address the challenges of functional correctness and optimization efficiency in automated hardware design using Large Lan-guage Models(LLMs),this paper presents VeriOptima,a two-stage framework that generates efficient gate-level netlists from natural language specifications.The first stage,ReasoningV,is a high-fidelity Verilog generation model that achieves 57.8%pass@1 accuracy on the VerilogEval-Human benchmark,rivaling state-of-the-art industry models.The second stage,CircuitMind,is a multi-agent opti-mization framework that refines the generated code to human-expert levels of efficiency.Evaluated on TC-Bench,a gate-level bench-mark derived from real design competitions,results show that using ReasoningV as a starting point and optimizing with CircuitMind leads to significantly better PPA metrics compared to other LLM-based flows.Ultimately,55.6%of the optimized implementations match or surpass the efficiency of top human experts.This work provides the first end-to-end solution that systematically overcomes both generation and optimization barriers,paving the way for fully automated,high-quality circuit design.Related code is open-sourced on GitHub.